Equivalence checking using independent cuts [logic design verification]

With the increase in the complexity of present day systems, proving the correctness of a design has become a major concern. This paper describes a novel implementation of a BDD-based combinational equivalence checking (CEC) tool, which is distinguished from others by one heuristic. It is proposed to select an effective cut, with no dependence remaining. In addition, successfully verification of all the ISCAS´85 benchmark circuits demonstrates the efficiency of our approach.