Design and Fabrications of High Voltage IGBTs on 4H-SiC

Author

Zhang, Qingchun ; Jonas, Charlotte ; Ryu, Sei-Hyung ; Agarwal, Anant ; Palmour, John

Author_Institution

Cree. Inc., Durham, NC

fYear

2006

fDate

4-8 June 2006

Firstpage

1

Lastpage

4

Abstract

For the first time, SiC planar p-IGBTs with 5.8 kV of blocking voltage have been fabricated and characterized. The device exhibits a differential on-resistance of ~ 570 mOmegamiddotcm² at the gate bias of -30 V at 25degC, and decreases to ~ 118 mOmegamiddotcm² at 200degC, ~108 mOmega middot cm ² at 300degC, respectively. The median hole mobility in the inversion channel is 2.3 cm²/Vmiddots, and increases gradually with temperature. The effects of p-type field stopper layer and JFET region implantation to device current conduction capability were investigated. Numerical simulations have shown that to improve IGBT on-resistance, it is critical to achieve a high carrier lifetime in both drift region and JFET region, and a high value of inversion layer hole mobility

Keywords

hole mobility; insulated gate bipolar transistors; power bipolar transistors; semiconductor device models; silicon compounds; wide band gap semiconductors; -30 V; 200 C; 25 C; 300 C; 5.8 kV; JFET region implantation; SiC; carrier lifetime; current conduction capability; differential on-resistance; high voltage IGBT; insulated gate bipolar transistors; inversion layer; median hole mobility; p-type field stopper layer; Buffer layers; Fabrication; Implants; Insulated gate bipolar transistors; MOSFET circuits; Numerical simulation; Silicon carbide; Substrates; Temperature; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Power Semiconductor Devices and IC's, 2006. ISPSD 2006. IEEE International Symposium on

Conference_Location

Naples

Print_ISBN

0-7803-9714-2

Type

conf

DOI

10.1109/ISPSD.2006.1666127

Filename

1666127