Impact of process variations on multi-level signaling for on-chip interconnects

Global interconnects are widely acknowledged as a limiting factor in future on-chip designs. Novel interconnect driving techniques like multi-level signaling have been proposed to improve performance of on-chip interconnects. This paper presents the impact of process-induced parameter variation on multi-level signaling system for on-chip interconnects. The effects of parameter variations is analyzed by Monte Carlo simulations and parameter sensitivity analyses. Monte Carlo analyses show that the threshold voltage, effective gate length and supply voltage are the key parameters that influence interconnect delay and total average power. It also shows that the interconnect delay and total average power with multi-level signaling for 10 mm line in 100 nm technology are normally distributed with a standard deviation of around 7.8% and 14.55% respectively. Individual parameter sensitivity analyses show that the total average power is most influenced by threshold voltage and is least influenced by drain/source parasitic resistance and thickness of oxide. The impact of different technologies, which include 180 nm, 130 nm and 100 nm are analyzed and it can be seen that the impact of individual device variation on delay and power reduces as technology scaled down. Yield of high performance and low power bins in 180 nm technology under process variations is 30%, yield of high performance bins is 23.2% and yield of low power bins is 36.1%.