Title :
A low-leakage SCR design using trigger-PMOS modulations for ESD protection
Author :
Morishita, Yasuyuki ; Okushima, Mototsugu
Author_Institution :
NEC Electron. Corp., Kawasaki
Abstract :
A low-leakage SCR design using trigger-PMOS modulations is proposed for ESD protection. By using the SCR design, a leakage current less than 10-13A was achieved together with a trigger voltage, VtI=1.8 V, and ESD performances 5.5 kV HBM and 300 V MM or over in our 65 nm CMOS technology. This design concept can be used for wide applications by changing the structure of the trigger-PMOS.
Keywords :
CMOS integrated circuits; electrostatic discharge; integrated circuit design; leakage currents; thyristors; CMOS technology; ESD protection; leakage current; low-leakage SCR design; trigger-PMOS modulations; voltage 300 V; voltage 5.5 kV; CMOS technology; Circuits; Diodes; Electrostatic discharge; Leakage current; Protection; Stress; Thyristors; Variable structure systems; Voltage;
Conference_Titel :
29th Electrical Overstress/Electrostatic Discharge Symposium, 2007. EOS/ESD
Conference_Location :
Anaheim, CA
Print_ISBN :
978-1-58537-136-5
DOI :
10.1109/EOSESD.2007.4401776
