Title :
RTL concurrent fault simulation
Author_Institution :
Inst. of Comput. Technol., Chinese Acad. of Sci., Beijing, China
Abstract :
The integrated circuit (IC) design has been pushed to hardware description language (HDL) description and high-level synthesis (HLS) techniques. The IC testing is also going to the high-level one. For the high-level testing, like gate level one, it needs a circuit model at high level such that, The model is easy to be converted and extended from the HDL descriptions. The model should be unified for multiple usages such as fault simulation, test generation, testability measure, etc. For various algorithms, it is easy to perform forward and backward tracing on the model, and easy to define fault models. In this paper, we try to construct such model and apply it to the fault simulation first.
Keywords :
fault simulation; hardware description languages; high level synthesis; integrated circuit design; integrated circuit testing; logic testing; RTL concurrent fault simulation; Verilog RTL Model; backward tracing; circuit modeling; fault model; forward tracing; hardware description language; high-level synthesis; high-level testing; integrated circuit design; one-pass process; test generation; testability measure; Chip scale packaging; Circuit faults; Circuit simulation; Circuit testing; Computational modeling; Hardware design languages; High level synthesis; High-level synthesis; Integrated circuit design; Integrated circuit modeling; Integrated circuit synthesis; Integrated circuit testing; Logic circuit testing; Semiconductor device measurement;
Conference_Titel :
Test Symposium, 2003. ATS 2003. 12th Asian
Print_ISBN :
0-7695-1951-2
DOI :
10.1109/ATS.2003.1250870
