Title :
Property classification for functional verification based on CDFG
Author :
Zhu, Ming ; Bian, Jinian ; Wu, Weimin ; Xue, Hongxi
Author_Institution :
Dept. of Comput. & Sci. Technol., Tsinghua Univ., Beijing, China
Abstract :
Based on the advantages of simulation and model checking with CDFG structure, classified properties are proposed and defined for simulation, CDFG matching, and model checking respectively. With ITC99 benchmarks, the designed properties are verified, and the experimental results show that different properties should be verified distinguishingly.
Keywords :
fault simulation; formal verification; hardware description languages; high level synthesis; temporal logic; CDFG structure; ITC99 benchmarks; VHDL; functional verification; model checking; property classification; simulation properties; temporal logic; Automatic logic units; Benchmark testing; Bridges; Computational modeling; Computer bugs; Computer simulation; Data structures; Discrete event simulation; Hardware design languages; High level synthesis; High-level synthesis; Reactive power; Temporal logic;
Conference_Titel :
Test Symposium, 2003. ATS 2003. 12th Asian
Print_ISBN :
0-7695-1951-2
DOI :
10.1109/ATS.2003.1250871
