Title :
Understanding the optimization of sub-45nm FinFET devices for ESD applications
Author :
Trémouilles, D. ; Thijs, S. ; Russ, C. ; Schneider, J. ; Duvvury, C. ; Collaert, N. ; Linten, D. ; Scholz, M. ; Jurczak, M. ; Gossner, H. ; Groeseneken, G.
Author_Institution :
CNRS, Toulouse
Abstract :
ESD performance of advanced FinFETs shows a delicate sensitivity to device layout and to processing. Thermal issues are experimentally correlated to gate length, fin width, electrical operation mode and are investigated by TCAD simulation. S/D implant conditions, silicide blocking, and selective epitaxial growth are studied. Reasonable ESD performance is demonstrated while margins between success and failure seem to be very narrow.
Keywords :
circuit optimisation; electrostatic discharge; field effect transistors; technology CAD (electronics); ESD applications; FinFET device optimization; TCAD simulation; electrical operation mode; fin width; gate length; selective epitaxial growth; silicide blocking; thermal issues; CMOS technology; Doping; Electrostatic discharge; Etching; FinFETs; Implants; Instruments; Robustness; Semiconductor films; Silicon;
Conference_Titel :
29th Electrical Overstress/Electrostatic Discharge Symposium, 2007. EOS/ESD
Conference_Location :
Anaheim, CA
Print_ISBN :
978-1-58537-136-5
DOI :
10.1109/EOSESD.2007.4401780
