DocumentCode
2368818
Title
Testability improvement during high-level synthesis
Author
Safari, Saeed ; Esmaeilzadeh, Hadi ; Jahangir, Amir-Hossein
Author_Institution
CE Dept., Sharif Univ. of Technol., Tehran, Iran
fYear
2003
fDate
16-19 Nov. 2003
Firstpage
505
Abstract
Improving testability during the early stages of High-Level Synthesis (HLS) reduces test hardware overheads, test costs, design iterations, and also improves fault coverage. In this paper, we present a novel register allocation algorithm which is based on weighted graph coloring, targeting testability improvement.
Keywords
design for testability; graph colouring; high level synthesis; logic testing; design iterations; extended conflict graph; fault coverage; greedy algorithm; high-level synthesis; register allocation algorithm; test costs; test hardware overheads; testability improvement; weighted graph coloring; Automatic test pattern generation; Automatic testing; Benchmark testing; Circuit faults; Circuit testing; Costs; Design for testability; Electrocardiography; Graph theory; High level synthesis; High-level synthesis; Logic circuit testing; Merging; Registers;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Symposium, 2003. ATS 2003. 12th Asian
ISSN
1081-7735
Print_ISBN
0-7695-1951-2
Type
conf
DOI
10.1109/ATS.2003.1250874
Filename
1250874
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