An efficient end to end design of Rijndael cryptosystem in 0.18 μ CMOS

The paper presents an ASIC design for AES-Rijndael cryptosystem in 0.18 μ CMOS technology. The memoryless pipelined architecture achieves a speed of 8 Gbps@250 MHz clock. The pipelined architecture can be made to toggle between the encryption and decryption modes without the presence of any dead cycle. The on-chip key scheduling has been made secured against external attacks. The performance has been compared with those of competitive architectures and exhibits its elegance in successfully optimizing the conflicting requirements of high throughput, less area and low power.