Dual Strained Channel co-integration into CMOS, RO and SRAM cells on FDSOI down to 17nm gate length

We hereby present for the first time a successful Dual Strained Channel On Insulator (DSCOI) planar co-integration of tensily strained SOI nFETs and compressively strained SiGe pFETs down to 17nm gate length with functional ring oscillators and 6T SRAM cells. Various Ge contents and growth templates (unstrained or strained SOI) were screened in order to optimize the trade-off between threshold voltage adjustment with a single metal gate and strain-induced mobility enhancement. In particular, we reach 106% mobility boost for nFETs on sSOI and 70% for co-integrated pFETs on Si_0.6Ge_0.4/sSOI, compared to SOI (E_eff=0.6MV/cm). Moreover, the symmetrically low V_th,n and V_th,p result in -39% propagation delays improvement compared to SOI at 0.9V supply voltage.