Simple D flip-flop behavioral model of ESD immunity for use in the ISO 10605 standard

Author

Guangyao Shen ; Khilkevich, Victor ; Sen Yang ; Pommerenke, David ; Aichele, Hermann ; Eichel, Dirk ; Keller, Chris

Author_Institution

Missouri S&T EMC Lab., Missouri Univ. of Sci. & Technol., Rolla, MO, USA

fYear

2014

fDate

4-8 Aug. 2014

Firstpage

455

Lastpage

459

Abstract

As the ESD stress is becoming more and more important for integrated circuits (ICs), the ability to predict IC failures becomes critical. In this paper, an 18 MHz D flip-flop IC is characterized and its behavioral model is presented. The resulting IC model is validated in the setup according to the ISO 10605 standard. A complete model of the setup combining the IC behavioral model and the passive parts of the setup is built to estimate the failure prediction accuracy in a totally simulated environment. The results show that the model can predict the triggering level with the error of less than 20%.

Keywords

ISO standards; electrostatic discharge; failure analysis; flip-flops; integrated circuit modelling; integrated circuit testing; D flip-flop IC; D flip-flop behavioral model; ESD immunity; ESD stress; IC behavioral model; IC failures; ISO 10605 standard; electrostatic discharge; failure prediction accuracy; frequency 18 MHz; integrated circuits; Clocks; Electrostatic discharges; ISO standards; Integrated circuit modeling; Predictive models; Voltage measurement;

fLanguage

English

Publisher

ieee

Conference_Titel

Electromagnetic Compatibility (EMC), 2014 IEEE International Symposium on

Conference_Location

Raleigh, NC

Print_ISBN

978-1-4799-5544-2

Type

conf

DOI

10.1109/ISEMC.2014.6899015

Filename

6899015