• DocumentCode
    2368959
  • Title

    Experimental Implementation and Characterization of a CMOS Compatible Buffered SJ-LDMOST

  • Author

    Il-Yong Park ; Salama, C.A.T.

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Toronto Univ., Ont.
  • fYear
    2006
  • fDate
    4-8 June 2006
  • Firstpage
    1
  • Lastpage
    4
  • Abstract
    The buffered SJ-LDMOST structure, implemented in a standard CMOS technology, has been demonstrated experimentally. The implementation involves the additional formation of the N-buffer and the pillars in a 0.8 mum CMOS process. The experimental breakdown voltage and the specific on-resistance for the buffered SJ-LDMOS are 87.5 V and 2.66 mOmegamiddotcm2, respectively. The buffered structure efficiently suppresses the substrate effects to achieve high breakdown voltage
  • Keywords
    MOSFET; buffer circuits; semiconductor device breakdown; semiconductor device models; 0.8 micron; 87.5 V; CMOS compatible buffered SJ-LDMOST; N-buffer; breakdown voltage; specific on-resistance; standard CMOS technology; CMOS process; CMOS technology; Conductivity; Electric breakdown; Implants; Ion implantation; Semiconductor devices; Strontium; Substrates; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Power Semiconductor Devices and IC's, 2006. ISPSD 2006. IEEE International Symposium on
  • Conference_Location
    Naples
  • Print_ISBN
    0-7803-9714-2
  • Type

    conf

  • DOI
    10.1109/ISPSD.2006.1666140
  • Filename
    1666140
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2368959