Author :
Monfray, S. ; Huguenin, J.L. ; Martin, M. ; Samson, M.P. ; Borowiak, C. ; Arvet, C. ; Dalemcourt, JF ; Perreau, P. ; Barnola, S. ; Bidal, G. ; Denorme, S. ; Campidelli, Y. ; Benotmane, K. ; Leverd, F. ; Gouraud, P. ; Le-Gratiet, B. ; De-Buttet, C. ; Pinze
Abstract :
We demonstrate for the first time high-performant planar multi-gates devices with Si-conduction channel of 4nm, allowing drive current up to 1350μA/μm @Ioff=0.4nA/μm (Vdd=1.1V, CET=1.9nm). But as future multi-gates transistors need to have reduced capacitances and a simple robust process, we also demonstrate in this paper an ideal planar self-aligned solution, based on the direct exposure of a HSQ layer through a 5nm Si-channel. This opens the way to an easy planar multi-gate process for ultimate CMOS (11nm node & below), fully co-integrable with conventional devices.
