LDMOSFETs with Current Diverter for Smart Power Technologies

In this paper we propose and demonstrate a novel NLDMOSFET device concept, designed for deep sub-micron smart power technologies. The proposed device is designed with a P+ current diverter in the LDMOS drain so as to create a base-collector shorted PNP bipolar transistor from the source to the drain terminal of the LDMOS. Due to the inherent gain associated with the PNP device, the proposed LDMOSFET diverts more current in to the source/body terminal during reverse current injection phase, thereby reducing the amount of current that can get injected in to the substrate. Both single and double resurf LDMOSFETs have been investigated and dramatic improvement in substrate injection suppression is observed with no loss in breakdown voltage. Proposed devices also demonstrated significantly enhanced robustness and safe operating area (SOA)