High Voltage (up to 20V) Devices Implementation in 0.13 um BiCMOS Process Technology for System-On-Chip (SOC) Design

Author

Pan, Robert ; Todd, Bob ; Hao, Pinghai ; Higgins, Robert ; Robinson, Derek ; Drobny, Vlad ; Tian, Weidong ; Wang, Jianglin ; Mitros, Jozef ; Huber, Mike ; Pillai, Sateesh ; Pendharkar, Sameer

Author_Institution

Texas Instruments Inc., Dallas, TX

fYear

2006

fDate

4-8 June 2006

Firstpage

1

Lastpage

4

Abstract

This paper describes the integration of the 20V complementary drain-extended MOS (DECMOS) and fully isolated drain-extended NMOS (DENMOS) transistors into a high-volume 0.13mum CMOS technology with two additional masks. The 20V devices were optimized for Rsp-BVdss performance without compromising the advanced 1.5V CMOS performance in the 0.35mum pitch copper, low-K dielectric process flow. This cost-effective process is very competitive for the power management (PM) chip design of portable devices

Keywords

BiCMOS integrated circuits; dielectric materials; integrated circuit design; system-on-chip; 0.13 micron; 0.35 micron; 1.5 V; 20 V; BiCMOS process technology; complementary drain-extended MOS; drain-extended NMOS transistors; low-K dielectric process flow; power management chip design; system-on-chip design; BiCMOS integrated circuits; CMOS process; CMOS technology; Copper; Isolation technology; MOS devices; MOSFETs; System-on-a-chip; Transistors; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Power Semiconductor Devices and IC's, 2006. ISPSD 2006. IEEE International Symposium on

Conference_Location

Naples

Print_ISBN

0-7803-9714-2

Type

conf

DOI

10.1109/ISPSD.2006.1666143

Filename

1666143