Efficient pipelined ADCs using integer gain MDACs

Power consumption of pipelined ADCs is a strong function of the number of bits resolved per stage, particularly for high-performance ADCs. Despite this, conventional design techniques continue to use interstage gain levels of 2^N which leave significant gaps in the design space, limiting the extent of optimization. This paper discusses a design method for arbitrary integer-valued interstage gain which retain all benefits of conventional schemes while optimizing power consumption. To demonstrate the practical benefits, a prototype 16-bit 20 Msps ADC with a target power consumption of 200 mW is designed using the proposed techniques.