DocumentCode :
2369129
Title :
Formation of vertical links in standard CMOS double-level metallizations by application of Nd:YAG- and excimer-laser radiation
Author :
Hartmann, H.-D. ; Hillmann-ruge, Th
Author_Institution :
Lab. fur Informationstechnol., Hannover Univ., Germany
fYear :
1991
fDate :
11-12 Jun 1991
Firstpage :
177
Lastpage :
184
Abstract :
Laser processing of vertical links has been studied on three different layer sequences with main emphasis on statistics. Experiments were carried out with a Nd:YAG and an excimer laser using a fixed number of pulses adapted to the layer sequence. Laser antifuses of different design and sizes were fabricated. Simple expanded interconnections of dimensions 10×10 μm2 (102), 142 and 202 (sequence 1 and 2) and 9.62, 12.62 and 19.52 (sequence 3) turned out to be best suitable. Applying two Nd:YAG pulses, maximum yield of 100% was obtained from 142 and 202-structures with low mean resistances Rm of 0.18 and 0.104 Ω, and a standard deviation σR of 0.145 and 0.06 Ω respectively. Yield obtained from 19.52 was 100% with Rm=0.219, and σR =0.199 Ω using 3 pulses and two contacts per structure. By application of two excimer pulses, maximum yield of sequence 2 was 100% obtained from 142- and 202-structures with Rm =0.125 Ω and 0.163 Ω and a σR of 0.095 and 0.12 Ω respectively. Application of three excimer pulses on 12.62-structures lead to a yield of 99.6% with Rm =0.552 and σR=0.357 Ω. In all yield evaluations, resistances ⩾3 Ω were treated as a failure
Keywords :
CMOS integrated circuits; VLSI; excimer lasers; integrated circuit technology; laser beam applications; metallisation; solid lasers; 9.6 to 20 micron; CMOS; VLSI; YAG:Nd laser pulses; YAl5O12:Nd; dimensions; double-level metallizations; excimer laser pulses; expanded interconnections; fixed number of pulses; laser antifuses; laser processing; layer sequences; statistics; vertical links; vertical via formation; Fuses; Laboratories; Logic testing; Metallization; Optical design; Optical pulses; Redundancy; Statistics; System testing; Timing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Multilevel Interconnection Conference, 1991, Proceedings., Eighth International IEEE
Conference_Location :
Santa Clara, CA
Print_ISBN :
0-87942-673-X
Type :
conf
DOI :
10.1109/VMIC.1991.152983
Filename :
152983
Link To Document :
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