Design of a current mode 6-bit 100 MS/s flash A/D converter with 0.75 pJ/conv-lev FoM

Author

Galdi, Ivano ; Bonizzoni, Edoardo ; Maloberti, Franco

Author_Institution

Univ. of Pavia, Pavia

fYear

2007

fDate

2-5 July 2007

Firstpage

69

Lastpage

72

Abstract

The design of a low-power 6-bit flash A/D converter with state-of-the-art figure of merit for flash architectures is presented. The target resolution with the lowest power consumption is achieved by using the voltage-to-current conversion strategy. The sampling frequency is 100 MHz and the proposed converter is able to work with an input signal frequency very close to Nyquist rate. Considering that the analog and the digital supply voltages are 1.8 V and 0.9 V, respectively, the achieved figure of merit is equal to 0.75 pJ/conv.

Keywords

analogue-digital conversion; low-power electronics; FoM; Nyquist rate; digital supply voltages; flash architectures; input signal frequency; low-power 6-bit flash A/D converter; power consumption; sampling frequency; voltage-to-current conversion strategy; CMOS technology; Costs; Delay; Energy consumption; Frequency conversion; Interpolation; Pipelines; Sampling methods; Signal resolution; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Research in Microelectronics and Electronics Conference, 2007. PRIME 2007. Ph.D.

Conference_Location

Bordeaux

Print_ISBN

978-1-4244-1000-2

Electronic_ISBN

978-1-4244-1001-9

Type

conf

DOI

10.1109/RME.2007.4401813

Filename

4401813