A fully-differential symmetrical OTA-based rail-to-rail switched buffer

Author

Stornelli, Vincenzo ; Ferri, Giuseppe ; De Marcellis, Andrea

Author_Institution

Univ. of L´´Aquila, L´´Aquila

fYear

2007

fDate

2-5 July 2007

Firstpage

85

Lastpage

88

Abstract

A CMOS low-voltage low-power switched OTA, optimized for its buffer configuration, suitable for both many portable applications and as input stage in digital architectures, is here presented. The circuit is a fully differential topology based on a symmetrical OTA featuring a rail-to-rail input and a reduced CMRR. It has been designed in a standard CMOS 0.35 mum technology and operates at 2V single supply voltage, showing a maximum power consumption of about 560 muW. Simulation results have confirmed the validity of the proposed architecture and have shown a -85dB THD for 100 kHz clock frequency, when a single tone input with lVpp amplitude at 10 kHz is applied.

Keywords

CMOS analogue integrated circuits; buffer circuits; integrated circuit design; low-power electronics; operational amplifiers; CMOS low-voltage low-power switched OTA; CMOS technology; CMRR; digital architectures; frequency 10 kHz; frequency 100 kHz; fully-differential symmetrical OTA; power 560 muW; rail-to-rail switched buffer; size 0.35 mum; switched op-amp; voltage 2 V; CMOS technology; Circuit topology; Energy consumption; Frequency; Low voltage; Operational amplifiers; Performance gain; Semiconductor optical amplifiers; Switches; Switching circuits; Rail-to-Rail Op-Amp.; Switched Buffer (SB); Switched Op-Amp (SOA);

fLanguage

English

Publisher

ieee

Conference_Titel

Research in Microelectronics and Electronics Conference, 2007. PRIME 2007. Ph.D.

Conference_Location

Bordeaux

Print_ISBN

978-1-4244-1000-2

Electronic_ISBN

978-1-4244-1001-9

Type

conf

DOI

10.1109/RME.2007.4401817

Filename

4401817