Optimizing the serialization factor in Networks-on-Chip: a case of study

Classic shared bus structures, traditionally used in MPSoC architectures, show functional and physical scalability issues, when the number of cores integrated on a single die increases. Network on Chip architectures are proposed as a solution to overcome this problems. The Aim of this paper is to discuss the relationship of the performances with respect to the mentioned interconnect parameters, in case of traffic generated by cache operations (block replacements). We paid special attention to investigate the impact of the serialization factor, that was already not clearly assessed in literature for this important case of study. A numerical analysis, referring to an actual implementation of the NoC on a state-of-the-art 65 nm technological process has been performed. The results were used to analyze how the energy and execution time metrics change over the whole design space. This allow the best choice of packet size and serialization factor value in order to optimize one or both metric.