A data parallel approach to Boolean function manipulation using BDDs

Author

Cabodi, G. ; Gai, S. ; Rebaudengo, M. ; Reorda, M. Sonza

Author_Institution

Dipartimento di Autom. e Inf., Politecnico di Torino, Italy

fYear

1994

fDate

2-6 May 1994

Firstpage

163

Lastpage

175

Abstract

The paper describes an Electronic CAD package exploiting the CM-200 architecture to manipulate boolean functions. The package exploits Binary Decision Diagrams (BDDs) to symbolically operate with boolean functions. The data parallel approach is based on distributing BDD nodes do the available Processing Elements and traversing BDDs in a breadth-first manner. The behaviour of the algorithm is studied and the results which have been obtained obtained for an application developed with the package are reported. They show that the approach exploits well the parallel hardware and is highly scalable; if implemented on state-of-the-art and fully configured systems, it could solve problems which can not be faced with conventional architectures

Keywords

Boolean functions; decision tables; logic CAD; logic design; parallel algorithms; BDDs; Boolean function manipulation; CM-200 architecture; Electronic CAD package; data parallel approach; Binary decision diagrams; Boolean functions; Central Processing Unit; Concurrent computing; Data structures; Electronic equipment testing; Electronics packaging; Memory management; Parallel algorithms; System testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Massively Parallel Computing Systems, 1994., Proceedings of the First International Conference on

Conference_Location

Ischia

Print_ISBN

0-8186-6322-7

Type

conf

DOI

10.1109/MPCS.1994.367081

Filename

367081