HW/SW FPGA implementation of Vector Median Filter

Author

Boudabous, A. ; Ben Atitallah, A. ; Kadionik, P. ; Khriji, L. ; Masmoudi, N.

Author_Institution

Lab. of Electron. & Inf. Technol., Sfax

fYear

2007

fDate

2-5 July 2007

Firstpage

101

Lastpage

104

Abstract

In this paper, we present an efficient hardware/software (HW/SW) implementation of the vector median filter (VMF) using embedded system for impulsive noise suppression in color image. The hardware portion including VMF algorithm is implemented with fast parallel architectures directly in hardware using VHDL language. The remaining parts were realized in software using NIOS II softcore processor using muClinux as operating system. The results show that the use of codesign implementation improves 48 times the filtering speed compared to the software solution.

Keywords

hardware description languages; hardware-software codesign; image colour analysis; median filters; VHDL language; embedded system; fast parallel architectures; hardware/software implementation; impulsive noise suppression; muClinux; operating system; vector median filter; Color; Colored noise; Embedded software; Embedded system; Field programmable gate arrays; Filtering; Filters; Hardware; Operating systems; Parallel architectures; FPGA; NIOS II softcore processor; SoPC; VMF; embedded system;

fLanguage

English

Publisher

ieee

Conference_Titel

Research in Microelectronics and Electronics Conference, 2007. PRIME 2007. Ph.D.

Conference_Location

Bordeaux

Print_ISBN

978-1-4244-1000-2

Electronic_ISBN

978-1-4244-1001-9

Type

conf

DOI

10.1109/RME.2007.4401821

Filename

4401821