Projection based fast passive compact macromodeling of high-speed VLSI circuits and interconnects

With the increasing operating frequencies and functionality in modern VLSI designs, the resulting size of circuit equations of high-frequency modules is becoming large. Two-level passive model-reduction based algorithms were recently suggested to obtain compact macro mode is for fast transient analysis of large scale VLSI circuits and interconnect networks. However, one of the major issues involved with the current second level reduction algorithms is the high computation expense. In order to overcome this difficulty, this paper describes an efficient algorithm for reducing the computational cost involved in second level passive reduction algorithms. Necessary formulation and validation examples are given.