DocumentCode
2369856
Title
A 0.2-2GHz 12mW multiplying DLL for low-jitter clock synthesis in highly-integrated data-communication chips
Author
Farjad-rad, R. ; Dally, W. ; Mg, H. ; Poulton, J. ; Stone, T. ; Rathi, R. ; Lee, E. ; Huang, D. ; Nathan, R.
Author_Institution
Velio Communications Inc.
Volume
2
fYear
2002
fDate
7-7 Feb. 2002
Firstpage
56
Lastpage
400
Keywords
Clocks; Error correction; Infrared detectors; Integrated circuit noise; Jitter; Noise generators; Phase detection; Phase frequency detector; Phase locked loops; Signal to noise ratio;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 2002. Digest of Technical Papers. ISSCC. 2002 IEEE International
Conference_Location
San Francisco, CA, USA
Print_ISBN
0-7803-7335-9
Type
conf
DOI
10.1109/ISSCC.2002.992107
Filename
992107
Link To Document