Title :
A combinational logic mapper for Actel´s SX/AX family
Author :
Chattopadhyay, Santanu ; Dewangan, Manas Kumar
Author_Institution :
Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Guwahati, India
Abstract :
This paper presents a technology mapper for combinational circuits targeting ActeVs SX-A/AX logic module. To the best of our knowledge, this is the first such effort reported in the literature. It exploits the module architecture completely to come up with good mapping solutions. In the absence of similar works, results have been compared with actl and act2 mappers and found to be encouraging.
Keywords :
application specific integrated circuits; combinational circuits; logic gates; logic testing; network synthesis; Actels SX/AX family; combinational circuits; combinational logic mapper; module architecture; technology mapper; Binary decision diagrams; Boolean functions; Data structures; Equations; Field programmable gate arrays; Libraries; Logic;
Conference_Titel :
VLSI Design, 2005. 18th International Conference on
Print_ISBN :
0-7695-2264-5
DOI :
10.1109/ICVD.2005.8
