DocumentCode
2370001
Title
Hot spots and zones in a chip: a geometrician´s view
Author
Majumder, S. ; Sur-Kolay, S. ; Nandy, S.C. ; Bhattacharya, B.B. ; Chakraborty, B.
Author_Institution
Int. Inst. of Inf. Technol., Kolkata, India
fYear
2005
fDate
3-7 Jan. 2005
Firstpage
691
Lastpage
696
Abstract
In this paper we have proposed geometric models that are employed to devise a scheme for identifying the hot spots and zones in a chip. These spots or zones need to be guarded thermally to ensure performance and reliability of the chip. Two different models, namely continuous and discrete, are presented to take into account whether the 2D plane of the chip floor is gridless or a uniform grid, thereby reflecting on the possible locations of heat sources and the target observation points. The experimental results for both the domains - continuous and discrete, establish that a region, which does not contain any heat source, may become hotter than other regions containing thermal sources. Thus a hot zone may appear away from the hot spots, and placing heat sinks on the active thermal sources alone may not suffice to tackle thermal imbalance.
Keywords
VLSI; heat sinks; integrated circuit modelling; integrated circuit reliability; 2D plane; chip reliability; continuous model; discrete model; geometric models; heat sources; hot spots; hot zones; thermal imbalance; Central Processing Unit; Circuits; Finite volume methods; Heat sinks; Information technology; Solid modeling; Temperature; Timing; Ultra large scale integration; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Design, 2005. 18th International Conference on
ISSN
1063-9667
Print_ISBN
0-7695-2264-5
Type
conf
DOI
10.1109/ICVD.2005.106
Filename
1383355
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