Title :
The impact of inductance on transients affecting gate oxide reliability
Author :
Nagaraj, N.S. ; Hunter, William R. ; Balsara, Poras ; Cantrell, Cyrus
Author_Institution :
Texas Instruments Inc., Dallas, TX, USA
Abstract :
Ringing due to inductance has an increased significance on gate oxide reliability (GOR), as failure rate is exponentially dependent on the effective voltage stress. Unlike lumped capacitance (C), self-inductance (L) itself has an impact on GOR failure rate. An added complexity in parasitic inductance extraction is that the inductance matrix is much larger than the capacitance matrix, as mutual inductance terms (K) decay slowly with distance. A comparative modeling study of the dependence of GOR failure rate on RC, RCL and RCLK effects is presented. A key finding from this study is that mutual inductance has a very large impact on GOR failure rate and needs accurate modeling. Methods to minimize GOR failure rate increases caused by parasitic inductance are discussed. This embedded tutorial covers the theory of Gate Oxide Reliability, mathematical approximations for estimating failure rates, theory of inductance modeling and a detailed study of the impact of inductance on GOR.
Keywords :
approximation theory; failure analysis; fault simulation; inductance; reliability theory; semiconductor device reliability; transients; GOR failure rate; gate oxide reliability; inductance impact; inductance matrix; inductance modeling theory; mathematical approximation; modeling accuracy; parasitic inductance extraction; self-inductance; transients; voltage stress; Circuits; Dielectric breakdown; Frequency; Inductance; MOS devices; Mutual coupling; Parasitic capacitance; Signal design; Stress; Voltage;
Conference_Titel :
VLSI Design, 2005. 18th International Conference on
Print_ISBN :
0-7695-2264-5
DOI :
10.1109/ICVD.2005.164