• DocumentCode
    2370414
  • Title

    Building a better butterfly: the multiplexed metabutterfly

  • Author

    Chong, Frederic T. ; Brewer, Eric A. ; Leighton, F. Thomson ; Knight, Thomas F., Jr.

  • Author_Institution
    MIT, Cambridge, MA, USA
  • fYear
    1994
  • fDate
    14-16 Dec 1994
  • Firstpage
    65
  • Lastpage
    72
  • Abstract
    Multistage networks are important in a wide variety of applications. Expander-based networks, such as multibutterflies, are a tremendous improvement over traditional butterflies in both fault and congestion tolerance. However, multibutterflies cost at least twice as much in chips and wiring as butterflies. It is also impossible to build large multibutterflies due to their wiring complexity. We show that we can build an expander-based network that has comparable cost to a butterfly with the same number of endpoints, yet has substantially better fault and congestion performance. Specifically, we introduce a hierarchical construction that dramatically reduces wiring complexity and makes large expanders buildable. We are able to exploit the hierarchical structure to find large numbers of logical wires to multiplex over a smaller number of physical wires. Since many of the wires in an expander-based network are used to provide alternate paths, not useful bandwidth, substantial multiplexing can be done without significantly degrading performance. We present simulation results to support our conclusions. In comparing a butterfly with the comparable 2-to-1 multiplexed metabutterfly, we found that the metabutterfly performed better by nearly a factor of two on random traffic and greater than a factor five on worst-case traffic
  • Keywords
    communication complexity; multistage interconnection networks; butterfly; congestion; fault; multiplexed metabutterfly; multistage networks; wiring complexity; Bandwidth; Contracts; Costs; Fault tolerance; Large scale integration; Logic; Multiprocessor interconnection networks; Parallel architectures; Wires; Wiring;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Parallel Architectures, Algorithms and Networks, 1994. (ISPAN), International Symposium on
  • Conference_Location
    Kanazawa
  • Print_ISBN
    0-8186-6507-6
  • Type

    conf

  • DOI
    10.1109/ISPAN.1994.367163
  • Filename
    367163