Parallel power grid analysis using distributed direct linear solver

Accurate and efficient power grid analysis has become increasingly important in semiconductors chip design and verification. It is one of the most computationally challenging tasks in high performance processor design analysis. Due to the extremely large memory required to store and manipulate the design data, it is no longer possible to accommodate the analysis using one or more serial processes on a single computer. The proposed method of large scale power grid analysis with sparse linear solver effectively distributes the computing tasks across multiple processes running on different computers within the network. It provides a stable, accurate, and scalable solution for the future process technology and design generations. The implementation incorporates advanced packages for matrix ordering, matrix factorization and solution, and message passing interface (MPI) integrated into the software tool capable of simulating extremely large scale design with billions of devices. The method can be applied to the power grid of arbitrary size and configuration, and produces results with SPICE-like accuracy. The benchmark analysis runs applied to the largest blocks of the latest Sparc processor design using 16 distributed processes demonstrate more than 6X memory utilization improvement and 9X performance improvement over a state-of-the-art serial solution currently employed in semiconductor industry.