SCINDY: logic crosstalk delay fault simulation in sequential circuits

A conventional approach to the simulation of crosstalk-induced delay faults is commonly centered around an electrical-level circuit simulation. While yielding high accuracy, the process is time-consuming and may no longer be feasible for modern, high-density VLSI circuits. To address this issue, we propose and develop a novel approach for gate-level simulation of crosstalk delay faults caused by coupling between aggressor and victim signal lines. Our algorithm extends existing fundamental principles of logic event-driven simulation to crosstalk delay faults excitation, injection, and verification. In addition, the simulator is capable of handling multiple-aggressors/single-victim faults in an efficient manner.