DocumentCode
2370702
Title
Stress induced void formation of the vias in the Al-based multi-level interconnection system
Author
Kanazawa, M. ; Shishino, M. ; Hata, Y. ; Umemoto, T.
Author_Institution
Kyoto Res. Lab., Matsushita Electron. Corp., Japan
fYear
1991
fDate
11-12 Jun 1991
Firstpage
221
Lastpage
227
Abstract
Effects of the stress induced void formation to submicron vias with the Al based multilevel interconnection have been investigated. In this study, vias with the conventional Al/Al interface and with the titanium interlayer were compared in terms of stress induced open failures. The investigated via diameter varied between 0.6 μm and 1.8 μm. It was found that conventional vias were opened during high temperature storage. Open failures occurred from the small vias and were caused by the passivation stress. In addition, it was considered that the crystal discontinuity of aluminum grain across the via interface enhanced open failures. The effect of the titanium interlayer at the via interface on the suppression of open failures could be caused by the intermetallic layer of Al3Ti. This intermetallic layer prevented the stress induced void formation of the aluminum conductor
Keywords
VLSI; aluminium alloys; metallisation; reliability; titanium; 0.6 to 1.8 micron; Al based multilevel interconnection; Al-Al; Al-Ti; VLSI multilevel interconnection; crystal discontinuity; high temperature storage; intermetallic layer; passivation stress; reliability issues; small vias; stress induced open failures; stress induced void formation; submicron vias; suppression of open failures; via diameter; Aluminum; Chemicals; Conductors; Integrated circuit interconnections; Passivation; Plasma applications; Plasma chemistry; Tensile stress; Testing; Titanium;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Multilevel Interconnection Conference, 1991, Proceedings., Eighth International IEEE
Conference_Location
Santa Clara, CA
Print_ISBN
0-87942-673-X
Type
conf
DOI
10.1109/VMIC.1991.152991
Filename
152991
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