Structural fault diagnosis in charge-pump based phase-locked loops

Author

Medury, AdityaSankar ; Carlson, I. ; Alvandpour, Atila ; Stensby, J.

Author_Institution

Dept. of Electr. & Comput. Eng., Alabama Univ., Huntsville, AL, USA

fYear

2005

fDate

3-7 Jan. 2005

Firstpage

842

Lastpage

845

Abstract

An approach is presented for identifying structural-faults, using the charge-frequency based built-in-self test (CF-BIST) technique in a phase-locked loop (PLL) circuit, for a standard 0.18 μm CMOS process. This method not only validated the CF-BIST approach for fault detection, but also showed an algorithm for how this approach may possibly be used for fault diagnosis as well, for a wide frequency PLL. The method of fault diagnosis is based on measuring the 8-bit digital values from the voltage-controlled oscillator (VCO)/Divide-by-N counter and performing comparisons between the values for the fault-free and fault-introduced conditions.

Keywords

CMOS integrated circuits; automatic testing; built-in self test; counting circuits; fault location; fault trees; integrated circuit testing; phase locked loops; voltage-controlled oscillators; 0.18 micron; 8 bit; 8-bit digital values; CF-BIST technique; CMOS process; Divide-by-N counter; PLL circuit; VCO; charge-frequency based built-in-self test; charge-pump based phase-locked loops; fault detection; fault-free condition; fault-introduced condition; structural fault diagnosis; voltage-controlled oscillator; wide frequency PLL; CMOS process; Charge pumps; Circuit faults; Circuit testing; Counting circuits; Electrical fault detection; Fault diagnosis; Frequency; Phase locked loops; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Design, 2005. 18th International Conference on

ISSN

1063-9667

Print_ISBN

0-7695-2264-5

Type

conf

DOI

10.1109/ICVD.2005.153

Filename

1383383