Title :
Design issues in switched capacitor ladder filters
Author :
Basu, Arindam ; Dhar, A.S.
Author_Institution :
Adv. VLSI Design Lab., Indian Inst. of Technol., Kharagpur, India
Abstract :
This paper describes the design of a switched capacitor ladder filter and explores the optimization of the opamps for reducing power consumption. A rough but quick optimization method of the opamp is suggested depending on the settling requirement for a desired accuracy. A method for approximately analyzing the noise in different types of switched capacitor circuits is also presented. The results are compared with simulations and exhibit a close match. A prototype filter has been laid out in a 0.25 μm process and has been sent for fabrication.
Keywords :
Butterworth filters; CMOS integrated circuits; circuit optimisation; integrated circuit design; ladder filters; operational amplifiers; switched capacitor filters; 0.25 micron; opamps; optimization method; power consumption reduction; switched capacitor circuits; switched capacitor ladder filters; Active filters; Circuit noise; Circuit simulation; Design optimization; Flow graphs; Frequency; Hydrogen; RLC circuits; Switched capacitor circuits; Very large scale integration;
Conference_Titel :
VLSI Design, 2005. 18th International Conference on
Print_ISBN :
0-7695-2264-5
DOI :
10.1109/ICVD.2005.72
