Title :
A diagonal interconnect architecture and its application to RISC core design
Author :
Igarashi, M. ; Mitsuhashi, T. ; Le, A. ; Kazi, S. ; Yang-Trung Lin ; Fujimura, A. ; Teig, S.
Author_Institution :
Toshiba Corporation
Keywords :
Clocks; Design methodology; Integrated circuit interconnections; Process design; Reduced instruction set computing; Routing; Semiconductor device modeling; Timing; Wire; Wiring;
Conference_Titel :
Solid-State Circuits Conference, 2002. Digest of Technical Papers. ISSCC. 2002 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-7335-9
DOI :
10.1109/ISSCC.2002.992196
