DocumentCode
2371098
Title
A two-stage pipelined architecture for parallel modular exponentiation
Author
Wu, Tao ; Li, Shuguo ; Liu, Litian
Author_Institution
Dept. of Microelectron. & Nanoelectron., Tsinghua Univ., Beijing, China
fYear
2012
fDate
23-25 March 2012
Firstpage
215
Lastpage
218
Abstract
In 1998, Koç and Hung proposed a modular multiplication algorithm with carry save additions, in which a sign-detection method in carry save logic is utilized. In this work, the carry save additions in their algorithm are divided into two pipelined stages, so that Montgomery ladder can be used to interleave two nearby modular multiplications. Efficient full modular exponentiation can be performed in such an architecture.
Keywords
carry logic; parallel processing; pipeline arithmetic; public key cryptography; Montgomery ladder; RSA cryptography; carry save additions; carry save logic; modular exponentiation; modular multiplication algorithm; parallel modular exponentiation; sign-detection method; two-stage pipelined architecture; Adders; Algorithm design and analysis; Clocks; Computer architecture; Hardware; Heuristic algorithms; Resistance;
fLanguage
English
Publisher
ieee
Conference_Titel
Information Science and Technology (ICIST), 2012 International Conference on
Conference_Location
Hubei
Print_ISBN
978-1-4577-0343-0
Type
conf
DOI
10.1109/ICIST.2012.6221640
Filename
6221640
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