Title :
Design and evaluation of fault-tolerant interleaved memory systems
Author :
Lu, Shyue-Kung ; Kuo, Sy-Yen ; Wu, Cheng-Wen
Author_Institution :
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Abstract :
A highly reliable interleaved memory system for uniprocessor and multiprocessor computer architectures is presented. The memory system is divided into groups. Each group consists of several banks and furthermore, each bank has several memory units. Spare memory units as well as spare banks are incorporated in the system to enhance reliability. Reliability figures are derived to evaluate systems with various amounts of redundancy. The result shows that the system reliability can be significantly improved with little hardware overhead. User transparency in memory access is retained
Keywords :
computer architecture; fault tolerant computing; interleaved storage; multiprocessing systems; reliability; design; fault-tolerant interleaved memory systems; memory access; memory system; multiprocessor computer architectures; overhead analysis; redundancy; reliability; spare banks; uniprocessor; user transparency; Bandwidth; Computer architecture; Contracts; Degradation; Fault tolerant systems; Hardware; Interleaved codes; Redundancy; System performance;
Conference_Titel :
Test Symposium, 1994., Proceedings of the Third Asian
Conference_Location :
Nara
Print_ISBN :
0-8186-6690-0
DOI :
10.1109/ATS.1994.367206
