Data path synthesis for easy testability

Synthesizing digital circuits which can be easily tested is an important and necessary aspect of a useful behavioral synthesis system. Testability at behavioral level can be enhanced by minimizing the number of self-adjacent registers (self-loops). This paper describes a technique for synthesizing an easy testable (loop-free) data path structure from a behavioral description of a design. The synthesis process uses an approach based on a problem-space genetic algorithm (PSGA) to perform concurrent scheduling and allocation of testable functional units to eliminate the self-loops. Experiments on benchmarks show that the self-loops can be eliminated with a minimum additional hardware resources to result in a testable data path