Title :
On full path delay fault testability of combinational circuits
Author :
Xie, Xiaodong ; Albicki, Alexander
Author_Institution :
Dept. of Electr. Eng., Rochester Univ., NY, USA
Abstract :
We show that robust tests for all path delay faults in a combinational circuit are not necessary in order to avoid test invalidation due to undesired hazards. Further extension leads to the formulation of the necessary and sufficient conditions for any path delay fault in a multi-level combinational circuit to be testable without potential invalidation by undesired hazards. We prove that all algebraic transformations and constrained resubstitution with complement are testability-preserving for the tests chosen
Keywords :
combinational circuits; delays; design for testability; fault diagnosis; logic design; logic testing; algebraic transformations; combinational circuit; combinational circuits; constrained resubstitution; delay fault testability; logic transformation; multilevel combinational circuit; path delay fault; path delay faults; reduced robust tests; two-level circuits; Circuit faults; Circuit synthesis; Circuit testing; Combinational circuits; Delay; Fault diagnosis; Hazards; Logic testing; Robustness; Sufficient conditions;
Conference_Titel :
Test Symposium, 1994., Proceedings of the Third Asian
Conference_Location :
Nara
Print_ISBN :
0-8186-6690-0
DOI :
10.1109/ATS.1994.367213
