Title :
Design verification by using universal test sets
Author :
Beyin Chen ; Lee, Chung Len ; Chen, Jwu E.
Author_Institution :
Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Abstract :
In this paper, the application of universal test sets (UTS) to design verification is studied. First, the paper analyzes the relationships between the design error models and the stuck-at fault model. Then theorems are presented to show that the UTS can detect almost all the design errors. Experimental results show that design verification using UTS is an efficient approach
Keywords :
automatic testing; fault location; logic design; logic testing; design error models; design verification; stuck-at fault model; universal test sets; wiring errors; Circuit faults; Circuit simulation; Circuit testing; Combinational circuits; Design engineering; Electrical fault detection; Electronic equipment testing; Fault detection; Wire; Wiring;
Conference_Titel :
Test Symposium, 1994., Proceedings of the Third Asian
Conference_Location :
Nara
Print_ISBN :
0-8186-6690-0
DOI :
10.1109/ATS.1994.367221
