Title :
Gate-level design diagnosis using a learning-based search strategy
Author :
Pomeranz, Irith ; Reddy, Sudhakar M.
Author_Institution :
Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
Abstract :
We propose a procedure for performing design error diagnosis at the gate level. The procedure is applicable to circuits having size parameters. It is based on the search strategy INCREDYBLE introduced before. The unique features of this procedure are that its performance does not deteriorate with circuit size, and that it is able to correct large numbers of errors present in the circuit at the same time. We demonstrate the procedure and provide experimental evidence of its effectiveness
Keywords :
fault diagnosis; fault location; learning (artificial intelligence); logic design; logic testing; search problems; INCREDYBLE; design error diagnosis; gate-level design diagnosis; learning-based search strategy; maximum circuit; sequence detector; Circuits; Cities and towns; Computer errors; Constraint optimization; Design optimization; Error correction; Process design;
Conference_Titel :
Test Symposium, 1994., Proceedings of the Third Asian
Conference_Location :
Nara
Print_ISBN :
0-8186-6690-0
DOI :
10.1109/ATS.1994.367222
