Evaluations of various TPG circuits for use in two-pattern testing

Author

FURUYA, KIYOSHI ; Yamazaki, Susumu ; Sato, Masayuki

Author_Institution

Dept. of Inf. & Syst. Eng., Chuo Univ., Tokyo, Japan

fYear

1994

fDate

15-17 Nov 1994

Firstpage

242

Lastpage

247

Abstract

Transition coverage has already been proposed as a measure of two-pattern test capabilities of TPG circuits for use in BIST. This paper investigates experimentally the relationships between transition coverages and actual stuck-open fault coverages in order to reveal what kind of circuits are appropriate for two-pattern testing. Fault simulation was performed using conventional (n-stage) LFSR, 2n-stage LFSR, and one-dimensional cellular automata (CAs) as TPG circuits and such sample circuits as balanced NAND tree and some ISCAS ´85 benchmark circuits as CUTs. It was found that CAs which are designed so as to apply exhaustive transitions to any 3-dimensional subspaces can detect high rate of stuck-open faults. Influence of hazards of decreasing the fault coverage is also mentioned

Keywords

NAND circuits; built-in self test; cellular automata; fault diagnosis; fault location; logic testing; shift registers; 2n-stage LFSR; 3-dimensional subspaces; BIST; ISCAS ´85 benchmark circuits; TPG circuits; balanced NAND tree; built in self test; exhaustive transitions; fault coverage; fault simulation; n-stage LFSR; one-dimensional cellular automata; stuck-open fault coverages; test pattern generation; transition coverage; transition coverages; two-pattern testing; Built-in self-test; Circuit faults; Circuit simulation; Circuit testing; Content addressable storage; Delay; Electrical fault detection; Fault detection; Hazards; Logic testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Symposium, 1994., Proceedings of the Third Asian

Conference_Location

Nara

Print_ISBN

0-8186-6690-0

Type

conf

DOI

10.1109/ATS.1994.367224

Filename

367224