• DocumentCode
    2371569
  • Title

    Design in fault isolating of ternary cellular arrays using ternary decision diagrams

  • Author

    Kamiura, Naotake ; Satoh, Hidetoshi ; Hata, Yutaka ; Yamato, Kazuharu

  • Author_Institution
    Dept. of Comput. Eng., Himeji Inst. of Technol., Hyogo, Japan
  • fYear
    1994
  • fDate
    15-17 Nov 1994
  • Firstpage
    201
  • Lastpage
    206
  • Abstract
    This paper proposes a method to design ternary cellular arrays with high testability. In it, stuck-at faults of switch cells are assumed. Testing of the array composed of switch cells can be executed easily because of the regular structure of the array. Moreover, if faulty cell is identified we can isolate the faulty cell from the remaining cells. The ternary functions represented by Ternary Decision Diagrams (TDD´s) are realized by mapping the TDD´s to the cellular arrays directly. Proposed arrays are more advantageous than ternary PLA´s for their sizes in realizations of symmetric functions and are also useful for the realizations of multiple-output functions
  • Keywords
    cellular arrays; cellular logic; decision tables; design for testability; logic design; ternary logic; mapping; multiple-output functions; regular structure; stuck-at faults; switch cells; symmetric functions; ternary cellular arrays; ternary decision diagrams; Boolean functions; Circuit faults; Circuit testing; Data structures; Design methodology; Integrated circuit interconnections; Logic arrays; Logic circuits; Programmable logic arrays; Switches;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Test Symposium, 1994., Proceedings of the Third Asian
  • Conference_Location
    Nara
  • Print_ISBN
    0-8186-6690-0
  • Type

    conf

  • DOI
    10.1109/ATS.1994.367230
  • Filename
    367230