DocumentCode
2371615
Title
On crosstalk fault detection in hierarchical VLSI logic circuits
Author
Liaud, A. ; Fourniols, J.-Y. ; Sicard, E.
Author_Institution
Inst. Nat. des Sci. Appliquees, Toulouse, France
fYear
1994
fDate
15-17 Nov 1994
Firstpage
182
Lastpage
187
Abstract
A realistic crosstalk fault detector operating at hierarchical layout and logic level is presented. A set of filtering schemes are proposed to reduce considerably the set of probable single and multiple coupling faults with details on substrate resistivity and unbalanced buffer implications. Comparisons between flat and hierarchical layout approaches are reported together with the performances of the tool for various IC implementations
Keywords
VLSI; crosstalk; fault diagnosis; integrated circuit noise; integrated circuit testing; integrated logic circuits; logic testing; crosstalk fault detection; double coupling crosstalk; filtering schemes; hierarchical VLSI logic circuits; multiple coupling faults; scaling down; single coupling faults; substrate resistivity; unbalanced buffer implications; CMOS technology; Capacitance; Circuit faults; Circuit testing; Crosstalk; Electrical fault detection; Integrated circuit modeling; Logic circuits; Very large scale integration; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Symposium, 1994., Proceedings of the Third Asian
Conference_Location
Nara
Print_ISBN
0-8186-6690-0
Type
conf
DOI
10.1109/ATS.1994.367234
Filename
367234
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