Real time implementation of the combined SLB/CA-CFAR system with non coherent integration

Author

Magaz, B. ; Bencheikh, M.L.

Author_Institution

R&D Center, Algiers

fYear

2008

fDate

21-23 May 2008

Firstpage

1

Lastpage

4

Abstract

In this paper, we present a real time DSP implementation of the combined cell averaging- constant false alarm rate (CA-CFAR) detector and sidelobe blanking (SLB) system with non coherent integration. The proposed approach has been implemented using the Texas Instruments TMS320C6713 processor. The designed architecture is fully reconfigurable in terms of the number of reference and guard cells as well as the sampling frequency and the coherent processing interval (number of integrated pulses). The data acquisition system can work under multimode including multi-range and different pulse width. The proposed system scheme and the real time implementation results are given in this paper.

Keywords

data acquisition; digital signal processing chips; signal detection; signal sampling; DSP; SLB/CA-CFAR system; cell averaging- constant false alarm rate; coherent processing interval; data acquisition; sidelobe blanking system; Blanking; Data acquisition; Detectors; Digital signal processing; Frequency; Instruments; Process design; Real time systems; Sampling methods; Space vector pulse width modulation; CA-CFAR; DSP; Implementation; Non Coherent Integration; SLB;

fLanguage

English

Publisher

ieee

Conference_Titel

Radar Symposium, 2008 International

Conference_Location

Wroclaw

Print_ISBN

978-83-7207-757-8

Type

conf

DOI

10.1109/IRS.2008.4585764

Filename

4585764