Easily testable realizations for generalized Reed-Muller expressions

Author

Sasao, Tsutomu

Author_Institution

Dept. of Comput. Sci. & Electron., Kyushu Inst. of Technol., Iizuka, Japan

fYear

1994

fDate

15-17 Nov 1994

Firstpage

157

Lastpage

162

Abstract

This paper presents a design method of easily testable AND-EXOR networks. It is an improvement of Reddy and Saluja-Reddy´s methods, and has the following features: 1) The network consists of a literal part, an AND part, an EXOR part, and a check part; 2) The EXOR part can be a tree instead of a cascade. Thus, the network is faster; 3) The network uses generalized Reed-Muller expressions (GRMs) instead of Positive Polarity Reed-Muller expressions (PPRMs). The number of products for GRMs is, on the average, less than a half of that for PPRMs, and is less than that of sum-of-products expression (SOPs); 4) The test detects multiple stuck-at-faults under the assumption that the faults occur in at most one part, either the literal part, the AND part, the EXOR part, or the check part

Keywords

design for testability; fault diagnosis; fault location; logic design; logic gates; logic testing; minimisation; AND part; EXOR part; check part; circuit complexity; fixed polarity; generalized Reed-Muller expressions; linear circuit; logic minimisation; multiple stuck-at-faults; testable AND-EXOR networks; tree; Circuit faults; Circuit testing; Complexity theory; Computer science; Design methodology; Electrical fault detection; Electronic equipment testing; Fault detection; Logic design; Logic testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Symposium, 1994., Proceedings of the Third Asian

Conference_Location

Nara

Print_ISBN

0-8186-6690-0

Type

conf

DOI

10.1109/ATS.1994.367237

Filename

367237