The effect of fault detection by IDDq measurement for CMOS VLSIs

Author

Hirase, Junich ; Hamada, Masanori

Author_Institution

Microcomput. Div., Matsushita Electron. Corp., Japan

fYear

1994

fDate

15-17 Nov 1994

Firstpage

144

Lastpage

149

Abstract

In the final stages of VLSI testing, improved quality VLSI testing is an important subject for ensuring reliability in the forwarded VLSI market. On the other hand, developments in high integration technology have resulted in an increased number of blocks in VLSI devices and an increased number of gates for each terminal. Consequently, it has become more difficult to improve the quality of VLSI tests. We have developed a new test method in addition to conventional testing methods intended for improving the test coverage in VLSI tests. This new test method analyzes the relationship between IDDq (Quiescent Power Supply Current) of DUT and DUT failure by applying the concept of the toggle rate. Accordingly, in this paper we report that the results of IDDq testing confirm a correlation with defect level

Keywords

CMOS integrated circuits; VLSI; electric current measurement; fault location; integrated circuit testing; CMOS VLSI; DUT failure; IDDq measurement; Quiescent Power Supply Current; VLSI testing; correlation; defect level; fault detection; high-speed testing; liability; stack at fault coverage; toggle rate; CMOS technology; Circuit faults; Circuit testing; Consumer electronics; Electrical fault detection; Electronic equipment testing; Fault detection; Logic testing; Microcomputers; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Symposium, 1994., Proceedings of the Third Asian

Conference_Location

Nara

Print_ISBN

0-8186-6690-0

Type

conf

DOI

10.1109/ATS.1994.367239

Filename

367239