Title :
A novel cylinder-type MIM capacitor in porous low-k film (CAPL) for embedded DRAM with advanced CMOS logics
Author :
Hijioka, K. ; Inoue, N. ; Kume, I. ; Kawahara, J. ; Furutake, N. ; Shirai, H. ; Itoh, T. ; Ogura, T. ; Kazama, K. ; Yamamoto, Y. ; Kasama, Y. ; Katsuyama, H. ; Manabe, K. ; Yamamoto, H. ; Saito, S. ; Hase, T. ; Hayashi, Y.
Author_Institution :
LSI Res. Lab., Renesas Electron. Corp., Sagamihara, Japan
Abstract :
A novel cylinder-type metal-insulator-metal (MIM) capacitor in porous low-k film (CAPL) is proposed for embedded DRAMs (eDRAMs). The CAPL removes long bypass-contacts (BCT) with high resistance, which have been used to connect transistors with Cu interconnects by way of the MIM capacitor layer. A key technical challenge for the CAPL integration is control of pore structure in the low-k film to avoid metal contamination during the gas-phase deposition of the MIM electrode (BE) on the porous low-k film. A molecular-pore-stack (MPS) SiOCH film (k=2.5) with very small pores (0.4 nm-diameter) is found to be the best candidate for the CAPL structure, applicable to eDRAM with high performance logics for 28 nm-node and beyond.
Keywords :
CMOS logic circuits; DRAM chips; MIM devices; capacitors; carbon; hydrogen; low-k dielectric thin films; silicon compounds; transistors; CMOS logics; SiOCH; bypass-contacts; copper interconnect; cylinder-type MIM capacitor; cylinder-type metal-insulator-metal capacitor; embedded DRAM; gas-phase deposition; metal contamination; molecular-pore-stack; porous low-k film; size 0.4 nm; size 28 nm; transistors;
Conference_Titel :
Electron Devices Meeting (IEDM), 2010 IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4424-7418-5
Electronic_ISBN :
0163-1918
DOI :
10.1109/IEDM.2010.5703469
