Title :
Random test input generation for supply current testing of TTL combinational circuits
Author :
Hashizume, Masaki ; Tsukimoto, Isao ; Tamesada, Takemomi
Author_Institution :
Fac. of Eng., Tokushima Univ., Japan
Abstract :
In this paper, a random test generation algorithm for supply current testing of TTL combinational circuits is proposed. In this method, by inserting equivalent faults first in the direction from the primary output ports to the primary input ports, the total number of fault simulations can be decreased. In this paper it is shown that test input vector can be derived more quickly by means of the algorithm
Keywords :
automatic testing; combinational circuits; electric current measurement; fault diagnosis; fault location; logic testing; random processes; transistor-transistor logic; TTL combinational circuits; equivalent faults; fault simulation; primary input ports; primary output ports; random test input generation; supply current testing; test input vector; Circuit faults; Circuit testing; Combinational circuits; Current supplies; Electrical fault detection; Fault detection; Logic circuits; Logic testing; Random number generation; System testing;
Conference_Titel :
Test Symposium, 1994., Proceedings of the Third Asian
Conference_Location :
Nara
Print_ISBN :
0-8186-6690-0
DOI :
10.1109/ATS.1994.367241
