Title :
Advanced flip-chip package production solution for 40nm/28nm technology nodes
Author :
Chen, S. ; Liu, C.S. ; Lee, C.H. ; Tsai, H.Y. ; Pu, H.P. ; Hsu, K.C. ; Kuo, H.J. ; Cheng, M.D. ; Wu, C.Y. ; Chiu, S.L. ; Wu, K.C. ; Chen, H.W. ; Hsiao, C.W. ; Tung, C.H. ; Lii, M.J. ; Yu, Douglas C H
Author_Institution :
R&D, Taiwan Semicond. Manuf. Co., Ltd., Hsinchu, Taiwan
Abstract :
The key technology challenges and solutions in the packaging and assembly of large dies and/or fine pitch on organic substrates for both the 40 and 28 nm technology nodes are reported. Both eutectic PbSn, Pb-free solders, and Cu pillar bumps were used in the flip chip packages. The key challenge of chip-package-integrations (CPI) due to the use of fragile extreme low-k (ELK) dielectric materials in the back-end-of-line (BEOL) layer has been resolved by the redesigning of the BEOL structure and optimizing the materials set including both the organic substrate and solder materials, along with process improvements.
Keywords :
dielectric materials; flip-chip devices; low-k dielectric thin films; advanced flip-chip package production solution; back-end-of-line layer; fine pitch; flip chip packages; fragile extreme low-k dielectric materials; organic substrates; size 28 nm; size 40 nm; technology nodes;
Conference_Titel :
Electron Devices Meeting (IEDM), 2010 IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4424-7418-5
Electronic_ISBN :
0163-1918
DOI :
10.1109/IEDM.2010.5703472
