Title :
Strained SiGe and Si FinFETs for high performance logic with SiGe/Si stack on SOI
Author :
Ok, I. ; Akarvardar, K. ; Lin, S. ; Baykan, M. ; Young, C.D. ; Hung, P.Y. ; Rodgers, M.P. ; Bennett, S. ; Stamper, H.O. ; Franca, D.L. ; Yum, J. ; Nadeau, J.P. ; Hobbs, C. ; Kirsch, P. ; Majhi, P. ; Jammy, R.
Author_Institution :
SEMATECH, Albany, NY, USA
Abstract :
In this work, we report high performance (Ion ~1 mA/μm at Ioff 100nA/μm @ 1V Vcc) short channel p-type SiGe/Si FinFETs combining high mobility, low Tinv (scaled High-k w/o Si cap), low Rsd, and process-induced strain. A dual channel scheme for high mobility CMOS FinFETs is demonstrated.
Keywords :
CMOS logic circuits; Ge-Si alloys; MOSFET; elemental semiconductors; silicon; silicon-on-insulator; SOI; Si; SiGe; dual channel scheme; high mobility CMOS FinFET; high performance logic; process-induced strain; short channel p-type FinFET;
Conference_Titel :
Electron Devices Meeting (IEDM), 2010 IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4424-7418-5
Electronic_ISBN :
0163-1918
DOI :
10.1109/IEDM.2010.5703474
